In the field of this invention it is known that for TDD HSDPA (High Speed Downlink Packet Access) a HS-DSCH (High Speed-Downlink Shared CHannel) transport channel can use QPSK (Quadrature Phase Shift Key) or 16 QAM (16-level
Quadrature Amplitude Modulation) modulation. In the case of 16 QAM modulation, 4 bits are mapped to a 16 level signal (composed of 4 in-phase levels and 4 quadrature levels). Two of the mapped bits have a higher reliability than the other two mapped bits (the bits to be modulated can thus be classified as being “high reliability bits” or “low reliability bits”).
HS-DSCH channel coding is known to use turbo codes. It is well known that performance of a turbo code can be improved if the systematic bits produced by the turbo coder are received with a greater reliability than the parity bits. It is thus natural to attempt to map the systematic bits from the output of the turbo coder to the “high reliability bits” within the 16 QAM constellation and the parity bits to the “low reliability bits” within the 16 QAM constellation. This scheme is known as “bit priority mapping”.
Bit priority mapping is known to be implemented for FDD (Frequency Division Duplex) HSDPA using a “HARQ (Hybrid Automatic-Repeat-Request) bit collection interleaver” followed by an “HS-DSCH interleaver”. The “HARQ bit collection interleaver” arranges the bits at the output of the physical layer hybrid ARQ (Automatic-Repeat-Request) functionality to achieve a preferential order of systematic bits at its output: the “HARQ bit collection interleaver” attempts to ensure that odd indexed bits are preferably systematic bits and even indexed bits are preferably parity bits.
The HS-DSCH interleaving stage interleaves the odd indexed and even indexed bits separately (in this way, the set of bits that are preferably systematic are kept separate from the set of bits that are preferably parity bits). In FDD HSDPA, the bits from the preferably systematic interleaver are mapped (in the physical channel mapping stage) to high reliability bits and the bits from the preferably parity interleaver are mapped to low reliability bits in the 16 QAM symbol.
In TDD, the physical channel mapping stage generally includes a function whereby odd indexed physical channels are filled with bits in a forward direction and even indexed physical channels are filled in the reverse direction. By filling odd indexed channels in the forward direction and even indexed channels in the reverse direction, an extra degree of interleaving is achieved. In general, the forwards/reverse mapping can be considered as a physical channel mapper interleaving function.
The TOD physical channel mapping scheme described above is suboptimal for HSDPA since it destroys the link between systematic bits and high reliability positions.
An alternative approach for physical channel mapping in TDD is to perform the identical operation to FDD: physical channels are all mapped in the forward direction consecutively (physical channel 1 is mapped in the forward direction; once this mapping is complete, left over bits are then mapped to physical channel 2 in the forward direction, etc.). This alternative approach will retain the benefit of mapping preferably systematic bits to high reliability bits and preferably parity bits to low reliability positions. However, this alternative approach does not give the interleaving benefit that is obtained from filling odd indexed physical channels in the forward direction and even indexed physical channels in the reverse direction.
A need therefore exists for channel mapping wherein the abovementioned disadvantage(s) may be alleviated.